This application is based on Japanese Patent Application No. HEI 10-340114, filed on Nov. 30, 1998, the entire contents of which are incorporated herein by reference.
a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having shallow junctions and silicide regions.
b) Description of the Related Art
High integration and high performance of semiconductor integrated circuits have been realized by using micro fine elements. Most of semiconductor integrated circuits have MOS transistors, particularly CMOS transistors. As the integration degree becomes high, concentration of an electric field near the drain becomes intense and the reliability is likely to be degraded. In order to relax this electric field concentration, a MOS transistor having a lightly doped drain (LDD) structure to be described hereinunder has been adopted.
An insulated gate electrode structure is first formed on a silicon substrate. By using this gate electrode as a mask, impurities are implanted lightly and shallowly in LDD regions. Thereafter, an insulating film is formed on the silicon substrate surface, covering the insulated gate electrode, and anisotropically etched to form side wall spacers on the side walls of the gate electrode. By using the insulated gate electrode structure and side wall spacers as a mask, impurity ions are implanted to form high impurity concentration source/drain regions.
After the two ion implantation processes, an annealing process is performed to activate the implanted impurity atoms. With the above processes, a MOS transistor having an LDD structure can be formed. A CMOS transistor having an LDD structure can be formed by performing ion implantation processes separately for an n-channel transistor and a p-channel transistor by using a resist mask or the like.
In order to realize a high performance of a transistor, it is desired to suppress a depletion region from being generated in a lower region of the gate electrode, to lower the source/drain resistance, and to lower the contact resistance of the source/drain region and gate electrode. In order to realize this, it is effective to activate implanted impurities at a high annealing temperature after the impurity ion implantation processes.
In order to suppress the short channel effect, it is desired to form the regions of the LDD structure having a low impurity concentration and p-n junctions thereof at a shallow depth from the substrate surface. In order to realize this, it is necessary to suppress diffusion of impurity ions (atoms) after they are implanted. In order to suppress the impurity diffusion, it is necessary to lower the annealing temperature for impurity activation.
A high annealing temperature is desired for the former requirements, whereas a low annealing temperature for impurity activation is desired for the latter requirements.
In order to improve the fundamental performances of a MOS transistor, the following conditions are necessary. In order to sufficiently activate impurities, an annealing temperature after the ion implantation processes is set high. In order to suppress the short channel effect, impurity ions are implanted to a shallow depth to form the LDD regions having the low impurity concentration at a shallow depth and in addition an annealing temperature for impurity activation is set low to suppress impurity diffusion.
It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of meeting both the requirements of a high annealing temperature and a low annealing temperature.
It is another object of the present invention to provide a method of manufacturing a semiconductor device having MOS transistors capable of forming LDD regions having shallow p-n junctions and reducing the resistance of main regions.
According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: (a) forming an insulated gate electrode structure on a surface of a silicon substrate; (b) laminating two or more films made of materials having different etching characteristics on the surface of the silicon substrate, the films covering the insulated gate electrode structure; (c) anisotropically etching two or more films made of different materials to form at least one film of one material covering the insulated gate structure and the silicon substrate and form side wall spacers on side walls of the insulated gate electrode structure, the side wall spacers being made of the remaining film or films of other material or materials; (d) implanting impurity ions into a surface layer of the silicon substrate by using as a mask the insulated gate electrode structure and the side wall spacers; (e) activating the implanted impurities to a first level; (f) removing the at-least-one film of one material by using as a mask the side wall spacers to expose an upper surface of the insulated gate electrode structure and a partial surface area of the silicon substrate; (g) forming a metal film capable of being silicided on the surface of the silicon substrate, the metal film covering the exposed surface of the silicon substrate and the insulated gate electrode structure; (h) performing a first silicidation reaction between the metal film and the exposed surface of the silicon substrate; (i) removing an unreacted portion of the metal film and the at-least-one film under the unreacted portion; (j) implanting impurity ions shallowly in the surface layer of the silicon substrate by using as a mask the insulated gate electrode structure; and (k) activating the shallowly implanted impurities to a second level lower than the first level to perform at a same time a second silicidation reaction for silicide formed by the first silicidation reaction.
Regions of the LDD structure having a high impurity concentration are first formed, and then regions of the LDD structure having a low impurity concentration are formed. The regions having the high impurity concentration are activated at a high annealing temperature to realize the low resistance of main regions. The regions having the low impurity concentration are activated at a low temperature to prevent p-n junctions from moving deep into the substrate.
The annealing process for forming shallow p-n junctions is performed by using a heat treatment for the silicidation reaction. It is therefore possible to form shallow p-n junctions and silicide regions with a simple process.
As above, shallow LDD p-n junctions can be formed so that an electric field concentration near the drain can be relaxed. The silicide regions connected to the high impurity concentration regions and gate electrode with low resistance can be realized. A high performance MOS transistor can therefore be provided.